Graphic Editor: Power-Down Design
This design example allows you to implement a battery-powered system’s power-down circuit using Altera® MAX® II devices.
The circuit in Figure 1 shows how an Altera EPM570-T100 CPLD with an external P-Channel MOSFET, diode(s), and resistors can be used to create a power-down system. The P-Channel MOSFET, or FET, controls the power supply from the battery to the CPLD and any other selected components in the system. The Gate of the FET is controlled by the CPLD and the switches in the application. The FET Gate is enabled when a switch is pressed. The CPLD has a small embedded timer that monitors switching activity and system activity, and once a specified period of inactivity is detected, the FET is disabled, powering down the CPLD and other components on the same power node.
Download the Power-Down design graphic editor and other files to support this implementation:
Figure 1. Block Diagram for Power-Down Circuit Using MAX II Devices
For more information on using this example in your project, see:
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