PLL Simulation Design Example
This design example demonstrates post-fit gate level timing simulation of an alt_pll megafunction configured using the MegaWizard® Plug-In Manager in Quartus® II software and implemented in an Altera® device. In this example you will
- Load an existing project in the Quartus II software (the megafunction is already created for you)
- Set up the project to generate the required netlist files for gate-level simulation in ModelSim®-Altera or ModelSim software
- Compile your design in the Quartus II software to generate a gate-level netlist
- Run the simulation with the scripts provided and understand the results
The design is created in Verilog HDL and consists of a top-level module (top) and a phase-locked loop (PLL) megafunction in Verilog named pll_example.v. For details on the alt_pll megafunction, refer to the altpll megafunction User Guide (PDF). Before running the example, make sure you have ModelSim or ModelSim-Altera software installed on your computer.
Download the pll_example.zip design example.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Using the Design Example
- Unzip the attached file to your desired location.
- Invoke the Quartus II software and load the top.qpf project.
- On the Assignments menu, click EDA Tool Settings to open the Settings dialog box and then click Simulation. Verify that ModelSim-Altera or ModelSim is selected in the Tool name field.
- On the Quartus II software toolbar, click compile. After compilation, the Quartus II software generates a post-fit netlist named top.vo (for use with the ModelSim software) in <project_dir>/simulation/modelsim. The SDF file (top_v.sdo), which is used for annotating delays in the gate-level timing simulation file, is also generated at the same location.
- Run the simulation by doing one of the following:
- To run the simulation using the Quartus II NativeLink feature, on the Tools menu, under EDA Simulation Tool, click Run EDA Gate Level Simulation.
- To run the simulation without the NativeLink feature, invoke the ModelSim-Altera/ModelSim software. Change the directory name to <project_dir>/simulation/modelsim.
To run the <project_dir>/simulation/modelsim/pll_ver.do script, type >do pll_ver.tcl in the simulator console window. You must use the +transport_int_delays and +transport_path_delays options in the pll_ver.tcl script to successfully perform the post-fit timing simulation.
Note: The NativeLink feature in the Quartus II software allows you to launch the ModelSim simulator from within the Quartus II software and start the simulation with just a few clicks of your mouse. To use the Quartus II NativeLink feature, you must also provide the absolute path for the ModelSim software (for example, C:\Modeltech_ae_61d\win32aloem). In the Quartus II software, on the Tools menu, click Options, then General, then EDA Tools Options. For more information on the NativeLink feature in the Quartus II software, refer to the chapter Mentor Graphics ModelSim Support (PDF) in volume 3 of the Quartus II Development Software Handbook.
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Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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