Simulation With the NativeLink Feature in Quartus II Software
You can use the NativeLink feature in Quartus® II software to facilitate the seamless transfer of information between Quartus II software and third-party simulators. This design example shows how to use the NativeLink feature in Quartus II software to perform functional or gate-level timing simulation of your design with third-party simulators. The Quartus II NativeLink feature allows you to launch your third-party party simulator from within the Quartus II software and run the simulation with just a few clicks of your mouse. All the library preparation and run commands are generated automatically by Quartus II software without requiring your input. All these actions are also stored in a script. The Quartus II NativeLink feature is supported by all the popular third-party simulators. This example demonstrates the use of the Quartus II NativeLink feature for ModelSim®-Altera® simulator. In this example, you will:
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Load an existing project in Quartus II software
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Set up the Quartus II project for the NativeLink feature and ModelSim-Altera tools
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Perform the functional (RTL) and gate-level timing simulations using the NativeLink feature
Note: This example was developed in Verilog HDL using Quartus II software version 7.1 and
ModelSim-Altera 6.1g running on a host with Windows XP SP2.
Using the Design Example
- Download the attached Quartus Project Archive (*.qar) file to your desired location.
- Load the nativelink_ex.qpf project into the Quartus II software.
- On the Assignments menu, click EDA Tool Settings to open the Settings dialog box and then click Simulation. Verify that ModelSim-Altera is selected in the Tool name field and click OK.
- To use the Quartus II NativeLink feature, you must also provide the absolute path for the ModelSim-Altera software:
- On the Tools menu, click Options, then General, then EDA Tool Options.
- In the EDA Tool Options pane specify the path to the ModelSim-Altera executable (for example, C:\altera\71\modelsim_ae\win32aloem).
- Set up NativeLink for your testbench:
- On the Assignments menu, click EDA Tool Settings and then select Simulation.
- In the Simulation settings dialog box, under NativeLink settings, select Compile test bench, then click Test Benches. The Test Bench dialog box appears.
- Select the testbench test and click Edit. (The settings shown are similar to the ones shown in Figure 1.) Click OK.
- Perform analysis and elaboration of your design:
- From the Processing menu, select Start and then click Start Analysis and Elaboration.
- Start RTL simulation:
- From the Tools menu, select EDA Simulation Tool and then click Run EDA RTL Simulation.
- To perform post-fit gate-level timing simulation of your design, compile your project by clicking the compile button in the Quartus II toolbar.
- After the compilation, perform the post-fit gate-level timing simulation:
- From the Tools menu, select EDA Simulation Tool and click Run EDA Gate Level Simulation.
Figure 1. Test Bench Dialog Box
Note: All the commands used to run the simulation are stored in scripts. In this example a ModelSim Macro File (*.do) is generated in the <project_directory>\simulation\modelsim directory while running NativeLink. You can perform a simulation with this *.do file if you are invoking ModelSim-Altera separately, that is, without using NativeLink.
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