Nios II C2H Acceleration Compiler FIR Design Example
This finite impulse response (FIR) design example demonstrates the use of the Nios® II embedded processor's C-to-Hardware Acceleration Compiler (C2H Compiler). In this example, the C2H Compiler accelerates a symmetric FIR filter of length 15 or 16 taps. This design example uses the full-featured example design from the Nios II Embedded Design Suite (EDS) as a baseline starting point.
A symmetric FIR filter reduces the number of multiplications by a factor of two, which can lead to significant speed improvement for a general-purpose processor. This improvement, however, is dramatically overshadowed by the performance improvements you can obtain by implementing this algorithm as a hardware accelerator. As a hardware accelerator, an algorithm is implemented as a specific-function circuit in the FPGA logic fabric. The C2H Compiler allows you to benefit from the parallelism available within FPGAs and, more importantly, allows you to quickly prototype various algorithms.
Like many FIR hardware accelerators, this implementation supports coefficient updating, which allows you to change the filter type. This implementation also supports both 15 and 16 taps, important for certain filter types where one has a preferred frequency response over the other. This design measures the performance of the software and hardware implementations of the FIR algorithm and displays the results via the console.
Hardware Design Specifications
Only software source files are provided with this design example. You can run this software on the full-featured hardware design example or any hardware design that contains the following components:
- Nios II processor core (Nios II/f core with data cache)
- 16-Mbytes+ memory (SDRAM)
- High-resolution timer (1ms resolution)
- Communication device (UART)
Note:
The FPGA must have 2kB of on-chip memory resources available to serve as a data buffer for the hardware accelerator. Timing requirements change as a result of including this additional accelerator hardware in the design.
The full-featured design is available with the Nios II EDS. If you do not have the Nios II EDS installed, you can download it for free.
Block Diagram
Figure 1. Parallel Symmetric FIR Accelerator Diagram
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C2H Compiler Acceleration Results
The C2H Compiler-accelerated FIR algorithm has at least 52x speed improvement compared to the same algorithm running on the fastest Nios II processor using full compiler optimization (-O3). This speed increase is due to the parallel implementation of the FIR algorithm. The speed increase differs depending on the memory used and the targeted PLD. Using a slower processor core, the hardware accelerator can approach up to three levels of magnitude speed improvement.
Download this Design Example
Download the Nios II C2H FIR Design Example (.zip file).
The .zip file contains all the necessary software files to reproduce the example, as well as a readme.txt file. The readme.txt file contains instructions for rebuilding the design targeting an existing hardware design.
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