Fast Nios II Hardware Design Example
This design example highlights the Nios® II processor's Dhrystone millions of instructions per second (MIPS) performance. The system achieves over 200 DMIPS in the Nios II /f core running on a Stratix® II device. The design can be used with three Nios II development kits: Stratix Edition, Stratix Professional Edition, and Stratix II Edition.
Using This Design Example
To obtain this design example, download a free evaluation version of the Nios II Embedded Design Suite (EDS). The example is installed in a directory under <Nios II EDS install path>/examples/verilog or /vhdl.
Design Specifications
- Board support: Nios II development kits (Stratix, Stratix Professional, Stratix II editions)
- Nios II core: Nios II /f, 4 Kbytes i-cache, 2 Kbytes d-cache
- JTAG debug module: Yes
- On-chip RAM: 64 Kbytes
- JTAG UART: 1
- Timer: 1
Related Links
Feedback
Did this information help you?
If not, please log onto mySupport to file a technical request or enhancement.
These Web Site Design Examples may be used within Altera Corporation devices only and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
|
Literature
> 
