Full-Featured Nios II Hardware Design Example
This design highlights many of the advanced features of the Nios® II processor. In addition to the features of the standard design, this design includes:
- A direct memory access (DMA) peripheral for high-speed data transfers
- A bit swap custom instruction connected to the Nios II CPU
- Execution trace enabled in the JTAG debug module
- A performance counter peripheral
- Tightly coupled data and instruction memories
This design is provided for all Nios II development kits.
Using This Design Example
To obtain this design example, download a free evaluation version of the Nios II Embedded Design Suite (EDS). The example is installed in a directory under <Nios II EDS install path>/examples/verilog or /vhdl.
Design Specifications
- Board support: Stratix®, Stratix Professional, Stratix II, Cyclone®, and Cyclone II editions
- Nios II core: Nios II /f, 4 Kbytes i-cache, 2 Kbytes d-cache
- JTAG debug module: Yes, hardware breakpoints, trace enabled
- On-chip RAM: 64 Kbytes (Stratix edition only)
- Off-chip RAM interface: 1 Mbyte
- Common flash interface (CFI) flash memory interface: 8 Mbytes
- SDRAM controller: 16 Mbytes
- DMA controller: 1
- JTAG UART : 1
- UART : 1
- Timer : 2
- Ethernet interface
- LED parallel I/O (PIO)
- 7-segment PIO
- Push-button PIO
- LCD interface
- System ID peripheral
- Performance counter
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These Web Site Design Examples may be used within Altera Corporation devices only and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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