Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Knowledge Database   |   Devices   |   Design Software   |   Intellectual Property   |   Design Examples   |   mySupport   |   Reference Designs  

 Products
      MAX/MAX II
      Stratix/Stratix GX
      Nios II
  
 Functionality
      Arithmetic
      Memory
      Bus & I/O
      Logic
      Interfaces & Peripherals
      DSP
      Communications
      PLL & Clocking
  
 Design Entry
      Quartus II Project
      Tcl
      VHDL
      Verilog HDL
      C Code Examples
      DSP Builder
      TimeQuest
  
 Simulation Tools
      Mentor Graphics ModelSim
      Cadence NCsim
      Synopsys VCS
  
 Legacy Examples
      Graphic Editor
      AHDL
  

Nios II High-Performance Example with Bridges

The Nios® II high-performance example illustrates how you can use bridges in your design to control the topology of your system. By controlling the system's topology, you can also increase the fMAX of your design.

This design example is based on the full-featured design provided in the Nios II Embedded Design Suite (EDS) and is enhanced to run at a higher clock speed without sacrificing features. Floating-point math hardware has been added to the design to accelerate single precision floating-point math operations.

Download high-performance full-featured ZIP (699 KB)

Design Specifications

  • Nios II/f core (with floating-point math hardware)
  • JTAG debug module (level 1)
  • On-chip tightly coupled data memory (8 Kbyte)
  • On-chip tightly coupled instruction memory (4 Kbyte)
  • DDR SDRAM controller (32 Mbyte)
  • SSRAM controller (2 Mbyte)
  • CFI flash memory interface (16 Mbyte)
  • DMA controller
  • EPCS controller (with bootloader)
  • JTAG UART
  • UART (RS-232)
  • Two timers
  • Ethernet interface
  • LED parallel I/O (PIO)
  • Seven-segment display PIO
  • Push-button PIO
  • LCD display interface
  • Performance counter
  • System ID peripheral

Figure 1. Nios II High-Performance Example with Bridges

Figure 1. Nios II High Performance Example With Bridges
View Full Size

Notes:

  1. TCIM = tightly coupled instruction master
  2. TCDM = tightly coupled data master
  3. RM = read master
  4. WM = write master

Performance

Nios II Development Kit Stratix® II RoHS Edition

  • 150-MHz clock frequency
  • 167 MIPS* (*Dhrystones 2.1 benchmark) with .text, .rodata, .rwdata in SSRAM and heap, stack in tightly coupled data memory

Nios II Development Kit Cyclone® II Edition

  • 100-MHz clock frequency
  • 107 MIPS* (*Dhrystones 2.1 benchmark) with .text, .rodata, .rwdata in SSRAM and heap, stack in tightly coupled data memory

Additional Designs

You can also refer to the Standard Nios II Hardware Design Example for the Nios II Embedded Evaluation Kit, Cyclone III Edition to see examples of where to add bridges to your design to increase system performance. 

Related Links


Feedback

Did this information help you?

If not, please log onto mySupport to file a technical request or enhancement.


These Website Design Examples may be used within Altera Corporation devices only and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.

 

 
Avalon Memory Mapped Bridges (PDF)

Literature: Nios II

Quartus II Handbook Volume 4: SOPC Builder

  Please Give Us Feedback