Low-Cost Nios II Hardware Design Example
This design takes advantage of Altera's low-cost Cyclone® device family's features and highlights the Nios® II processor's ability to use the EPCS serial configuration device to store program data. This design is provided for the Nios II Development Kit, Cyclone Edition.
Using This Design Example
To obtain this design example, download a free evaluation version of the Nios II Embedded Design Suite (EDS). The example is installed in a directory under <Nios II EDS install path>/examples/verilog or /vhdl.
Design Specifications
- Board support: Cyclone and Cyclone II editions
- Nios II core: Nios II /e, no cache
- JTAG debug module: Yes
- On-chip RAM: 4 Kbytes
- EPCS serial flash device: Yes
- SDRAM controller: 16 Mbytes
- JTAG UART: 1
- LED parallel I/O (PIO): Yes
- 7-segment PIO: Yes
- Push-button PIO: Yes
- System ID peripheral: Yes
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These Web Site Design Examples may be used within Altera Corporation devices only and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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