The small Nios® II hardware design example is based on the Nios II /e core and demonstrates the smallest possible working Nios II system. The processor boots from a small block of on-chip memory and uses a parallel I/O (PIO) peripheral to drive off-chip LEDs.
This design is a good starting point for using the Nios II processor for minimal control applications. This design is provided for the Stratix®, Stratix Professional, Stratix II, Cyclone®, and Cyclone II editions of the Nios II development kit.
Using This Design Example
To obtain this design example, download a free evaluation version of the Nios II Embedded Design Suite (EDS). The example is installed in a directory under <Nios II EDS install path>/examples/verilog or /vhdl.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Design Specifications
- Board support: Stratix, Stratix Professional, Stratix II, Cyclone, and Cyclone II editions
- Nios II core: Nios II /e, no cache
- JTAG UART: Yes
- JTAG debug module: No
- On-chip RAM: 2 Kbytes
- LED PIO: Yes
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Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
