The standard Nios® II hardware design example provides a mix of peripherals and memories similar to a typical Nios II processor system. The SOPC Builder system automatically generates an interface to each hardware component on the Nios II development board, such as SDRAM, LEDs, push buttons, and an Ethernet MAC/PHY. You can use the standard design as a starting point for your own embedded system by adding or removing components to meet your custom requirements. This design is provided for the following Nios II development kits:
Nios II Development Kit, Stratix II and Cyclone II Edition Standard Design Example
To obtain this design example, download a free evaluation version of the Nios II Embedded Design Suite (EDS). The example is installed in a directory under <Nios II EDS install path>/examples/verilog or /vhdl.
The use of this design is governed by, and subject to, the terms and conditions of the Altera® Hardware Reference Design License Agreement.
Design Specifications
- Board support: Nios II Development Kit, Stratix II and Cyclone II Editions
- Nios II core: Nios II /s, 4 Kbytes d-cache
- JTAG debug module
- On-chip RAM: 64 Kbytes (Stratix only)
- Off-chip RAM: 1 Mbyte
- Common flash interface (CFI) flash memory interface: 8 Mbytes
- EPCS serial flash device
- SDRAM controller: 16 Mbytes
- JTAG UART: 1
- UART: 1
- Timer: 2
- Ethernet interface
- LED parallel I/O (PIO)
- 7-segment PIO
- Push-button PIO
- LCD screen interface
- System ID Peripheral
Nios II Embedded Evaluation Kit, Cyclone III Edition Standard Design Example
Download this design and unzip it onto your hard drive. The design is also provided with the Nios II Embedded Evaluation Kit, Cyclone III Edition.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Design Specifications
- Board support: Nios II Embedded Evaluation Kit, Cyclone III Edition
- Nios II core: Nios II /f, 2 Kbytes d-cache, 4 Kbytes i-cache
- JTAG debug module
- Off-chip RAM: 1 Mbyte
- Common flash interface (CFI) flash memory interface: 8 Mbytes
- SDRAM controller: 32 Mbytes
- JTAG UART: 1
- Timer: 2
- LED parallel I/O (PIO)
- Push-button PIO: Yes
- System ID Peripheral
- Performance Counter
- Remote Update Block
- Avalon®-MM Pipeline Bridge : 2
- Avalon-MM Tri-State Bridge
- Avalon-MM Clock Crossing Bridge: 2
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Design Examples Disclaimer
These design examples may only be used within Altera devices and remain the property of Altera Corporation. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
