Standard Nios II Hardware Design Example
The standard Nios® II hardware design example is based on the Nios II /s processor core and provides a mix of peripherals and memories similar to a typical Nios II processor system. The SOPC Builder system automatically generates an interface to each hardware component on the Nios II development board, such as SDRAM, LEDs, an RS-232 connector, and an Ethernet MAC/PHY.
The standard design can be used as a starting point for your own embedded system by adding or removing components to meet your custom requirements. This design is provided for all Altera® Nios II development kits.
Using This Design Example
To obtain this design example, download a free evaluation version of the Nios II Embedded Design Suite (EDS). The example is installed in a directory under <Nios II EDS install path>/examples/verilog or /vhdl.
Design Specifications
- Board support: Stratix®, Stratix Professional, Stratix II, Cyclone®, and Cyclone II editions
- Nios II core: Nios II /s, 4 Kbytes d-cache
- JTAG debug module: Yes
- On-chip RAM: 64 Kbytes (Stratix only)
- Off-chip RAM: 1 Mbyte
- Common flash interface (CFI) flash memory interface: 8 Mbytes
- EPCS serial flash device: Yes (Cyclone only)
- SDRAM controller: 16 Mbytes
- JTAG UART: 1
- UART: 1
- Timer: 2
- Ethernet interface: Yes
- LED parallel I/O (PIO): Yes
- 7-segment PIO: Yes
- Push-button PIO: Yes
- LCD screen interface: Yes
- System ID peripheral: Yes
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These Web Site Design Examples may be used within Altera Corporation devices only and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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