This example contains an optimized time-domain finite impulse response (FIR) filter kernel based on the HPEC Challenge Benchmark suite. FIR filters can be implemented efficiently on an FPGA by using shift registers to maximize data reuse. This example demonstrates how to efficiently describe a FIR filter in Open Computing Language (OpenCLTM), which is part of the class of applications that use sliding windows. The specific computation implemented in this example is a 128-tap complex single-precision floating-point time-domain FIR filter.
FIR Filter Performance
|BittWare S5-PCIe-HQ D8||170|
- Efficient 1D sliding window buffer
- Single work-item kernel
- Detailed optimization guide (see the Downloads section)
- Third-party benchmark
The design example provides source code for the OpenCL device (.cl) as well as the host application. For compiling the host application, the Linux package includes a Makefile and the Windows package includes a Microsoft Visual Studio 2010 project.
The following downloads are provided for this example:
- v14.1 x64 Linux package (.tgz)
- v14.1 x64 Windows package (.zip)
- Time-Domain FIR Filter Optimization Guide (PDF)
The use of this design is governed by, and subject to, the terms and conditions of the Altera hardware reference design license agreement.
Software and Hardware Requirements
This design example requires the following tools:
- Altera Complete Design Suite (ACDS) v14.0 or later
- Altera SDK for OpenCL* v14.0 or later
- On Linux: GNU Make and gcc
- On Windows: Microsoft Visual Studio 2010
To download the Altera tools, visit the OpenCL download page. The requirements for the underlying operating system are the same as those of the Altera SDK for OpenCL.
Packages are available for older versions of the Altera SDK for OpenCL. Please note that these packages may not work with newer versions.
Downloads for the Altera SDK for OpenCL v14.0:
Downloads for the Altera SDK for OpenCL v13.1:
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.