The altpll_reconfig Megafunction User Guide provides two design examples to illustrate the frequency division and pulse width modulation using the altpll_reconfig megafunction. These two design examples use the MegaWizard® Plug-In Manager in the Quartus® II software. The steps to generate the megafunction using the MegaWizard Plug-In Manager are described in detail in the User Guide.
Example 1: Frequency Division
This design example illustrates how to reconfigure the c0 counter using the altpll_reconfig megafunction to vary the frequency of the same by changing the divide by value. The formula for changing the divide by value for different phase-locked loop (PLL) output frequencies is as below:
Divide by value = (((Fin * m) / n) / Fout) / 2
Where
Divide by value = High time count = Low time count
Fin = Input frequency
m = m Modulus value
n = n Modulus value
Fout = Required output frequency
In this example you change the output frequency of c0 from 100 MHZ to 50 MHZ by changing the divide by value from 3 to 6. The block diagram description of the division process is illustrated in Figure 1.
Figure 1: Frequency Division Using altpll_reconfig
The following design files are used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Design Example 2: Pulse Width Variation Using altpll_reconfig
This design example describes how to reconfigure the c1 counter using the altpll_reconfig megafunction to vary the pulse width of the same by changing the high count and low count value. The design example illustrates the change in pulse width from 50-50 percent to 25-75percent and then to 75-25 percent. The formula for changing the duty cycle is as follows:
Duty cycle = (Ch /Ct) % high time count and (Cl /Ct) % low time count with RSELODD = 0
Where
Ch = High time count
Cl = Low time count
Ct = Total time
When you set RSELODD = 1, you subtract 0.5 cycles from the high time and you add 0.5 cycles to the low time.
Example:
Ch = 2 cycles
Cl = 1 cycle
Since RSELODD = ‘1’ effectively changes the Ch and Cl to:
High time count = 1.5 cycles
Low time count = 1.5 cycles
Duty cycle = (1.5/3) % high time count and (1.5/3) % low time count
Figure 2: Pulse Width Variation Using alltpll_reconfig
The following design files are used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
