The altpll Megafunction User Guide offers two design examples that use the altpll megafunction to:
- Generate an external differential clock from an enhanced PLL (as shown in Figure 1)
- Generate and modify internal clock signals (as shown in Figure 2)
The following downloadable projects and files are used in this example:
- ddr_clk.zip (incomplete Quartus II project)
- shift_clk.zip (incomplete Quartus II project)
- completed ddr_clk and shift_clk Quartus II projects
- README file
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Figure 1. Completed DDR_CLK.bdf Diagram
Figure 2. Completed shift_clk.bdf Diagram
For more information on using this example, go to:
- altpll Megafunction User Guide
- Quartus II Software Help
- How to Use Quartus II Design Examples
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
