Quartus Design Example: Multiple-Match CAM (altcam)
A multiple-match content addressable memory (CAM) block allows duplicate data values to be stored at different address locations in the CAM block. This example implements a MegaWizardTM-generated fast multiple-match CAM block with 64 32-bit words.
Multiple match CAM blocks have two address matching schemes: unencoded and encoded. In the case of the 64x32 CAM example the unencoded match address is a 64-bit bus (mbits[63..0]). When the CAM block matches an input data value to an address location, it will assert each bit of the mbits bus that corresponds to a match address. For example, if there is a match at address locations 1 and 5, bits 1 and 5 of the mbits bus will drive high. The unencoded address is valid two clock cycles after a data input is applied to the CAM block.
A 64-word encoded CAM block outputs a 6-bit (log2(64)) encoded match address (maddress[5..0]). The maddress bus displays the match address for an input pattern. The mcount[5..0] signal indicates how many matches are found. If mcount is greater than one, mnext should be asserted to view the next match address.
The design and simulation files used in this example can be downloaded by clicking on the link below.
Download multiple_match.exe
Reading from an Initialized Multiple-Match CAM Block
CAM blocks can be initialized with a Hexadecimal file (.hex) with a memory initialization file (.mif), or you directly write to a CAM block. Figure 1 shows a simulation example for a CAM block that has been initialized with a MIF file. This example illustrates a pre-loaded CAM block that matches the data value of 5 at address locations 0, 8, and 16, followed by a CAM miss and a single CAM hit at maddress = 9 for data value 91.
Figure 1. Vector Waveform File (read.vwf) Illustration
A read is initiated by driving the write enable signal (wren) low and asserting the mstart signal. The pattern input signal must be held high for at least two clock cycles, and the mstart input signal must be held high for one clock cycle. Two clock cycles after mstart is registered the mcount signal reflects how many matches were found in the CAM block.
The mbits unencoded output will be valid one clock cycle after mstart is asserted. The mbits output does not require the use of the mnext signal. To view the matching addresses on maddress, assert the mnext signal, not more than two clock cycle after mstart.
Note:
This simulation example assumes that the CAM block was pre-loaded with initial.mif.
Writing to a Multiple-Match CAM Block
Figure 1 shows the process of writing to a 64-word CAM block.
A write operation is performed by asserting the wren and write address (wraddress) signals for two clock cycles. In this example, the data values of 9 and 18 are written into the CAM block at address locations 0 and 1, respectively.
Altera's CAM blocks also have support for "don't care" bits. The simulation example illustrates writing "don't care" values to address location 2. "Don't care" write operations require three clock cycles to complete. The wrxused signal is asserted and held for three clock cycles to indicate that the CAM block will be writing a "don't care" value. Any bits in the wrx bus that are set to 1 indicate that bit position will be a "don't care" bit.
Figure 2. Vector Waveform File (write.vwf) Illustration
The above example writes a value of 15 (HEX "0000000F") to address location 2 and it sets a "don't care" value of 240 (HEX "000000F0") at location 2. Therefore, all values of "000000XF" will produce a match at location 2 (where 0 < X < F). This scenario is illustrated in the write.vwf simulation where patterns 255 and 239 drive maddress to 2.
Deleting a value from the CAM Block
Word values can be deleted from a CAM block through the wrdelete signal. To delete a value, wren and wrdelete should be held high for two clock cycles, during which wraddress should indicate the address containing the word that will be deleted. See Figure 3.
The delete.vwf simulation writes a value of 9 at address location 0. This value is then deleted by asserting wren and wrdelete for 2 clock cycles while wraddress = 0. The data value 9 no longer produces a match after the delete operation.
A delete operation is equivalent to setting a never match address. The address location that is a deleted never matches an input pattern until a data value is subsequently written to the CAM block at that address location.
Figure 3. Vector Waveform File (delete.vwf) Illustration
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