FPGA, CPLD, and ASIC solutions from Altera
  • Download Center
  • Literature
Sign in/register
myAltera Account
Welcome
  •   myAltera
  •   Logout
  • Products
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
    • Literature
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • DSP
    • External Memory
    • Embedded Processing
    • Transceivers
    • Parallel I/O
    • Signal Integrity
    • System Integration
  • Training
    • Training Courses
    • University Program
    • Webcasts & Videos
    • Demonstrations
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Database
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • User Communities/Forums
    • mySupport
  • About Altera
    • About Us
    • Environmental
    • Customer Successes
    • Partners
    • Newsroom
    • Investor Relations
    • Jobs
    • Contact Us
  • Buy Online
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
  • Entire Site
  • Part Number
  • Knowledge Database
  • Support & Technical Docs
  • Forums & Wiki
Username:  
Password:  
 
Forgot my username or password
Don't have myAltera account? Register Now.
Enter your email address:

Quartus II Design Examples

Home > Support > Design Examples > Quartus II Project

The following examples provide instructions for implementing various functions using Altera® Quartus® II design software. For more information about the different design entry methods, refer to the Quartus II Software Help.

Quartus II Projects

  • Examples for altpll Megafunction User Guide
  • Examples for altmult_add Megafunction User Guide New
  • Examples for altdq_dqs Megafunction User Guide New
  • Examples for altpll_reconfig Megafunction User Guide New
  • Examples for altfp_add_sub Megafunction User Guide New
  • Examples for alt_ufm Megafunction User Guide New
  • Examples for lpm_shiftreg Megafunction User Guide New
  • Single-Match Content-Addressable Memory (CAM) (altcam)
  • Fast-Multiple Match CAM (altcam)
  • Multiple-Match CAM (altcam)

Quartus II Features

  • Design Space Explorer (DSE) Design Example

Quartus II Third-Party Verification Tool Flows

  • Quartus II Formal Verification flow with Cadence Conformal (LEC) Tool  New

How to Use Quartus II Design Examples

These design examples contain links to a downloadable executable file (.exe),  zipped file (.zip), or Quartus II project archived (.qar) file. These files contain all of the necessary design and project files to use the example. To use the examples, perform the following steps:

  1. Select the download link
  2. Save the file to your hard disk
  3. Run the .exe or extract the .zip/.qar

If the project is a Quartus file:

  1. Open the Quartus II software and choose Open Project (from the File menu)
  2. Select the design example <filename>.quartus file

If the project is a QAR file:

  1. Open the Quartus II software and choose Restore Archived Project (from the Project menu)
  2. In the Archive Name field, browse to the design example <filename>.qar file
  3. In the Destination Folder field, browse to a destination folder
  4. Select OK

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.

Rate This Page


  • Products
    • MAX/MAX II
    • Stratix/Stratix GX
    • Nios II
  • Functionality
    • Arithmetic
    • External Memory Interfaces
    • On-Chip Memory
    • Bus & I/O Functions
    • Logic
    • Interfaces & Peripherals
    • DSP
    • Communications
    • PLL & Clocking
  • Design Entry
    • Quartus II
    • Tcl
    • VHDL
    • Verilog HDL
    • C Code
    • DSP Builder
    • TimeQuest
    • On-Chip Debugging
      • SignalTap II
  • Simulation Tools
    • Mentor Graphics ModelSim
    • Cadence NCsim
    • Synopsys VCS
  • Legacy Examples
    • Graphic Editor
    • AHDL
    Please give us feedback
    Products | End Markets | Technology | Training | Support | About Altera | Buy Online
    Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
    Copyright © 1995-2010 Altera Corporation. All Rights Reserved.
    Altera Forum
    Altera
    Forum
    Twitter
    Twitter
    RSS
    RSS
    Facebook
    Facebook
    Flickr
    Flickr
    YouTube
    YouTube
    Email Updates
    Email
    Updates