This example implements a MegaWizard®-generated CAM block with 64 32-bit words.
Single-match CAM blocks have two address matching schemes: unencoded and encoded. In the case of the 64x32 CAM example the unencoded match address is a 64-bit bus (mbits[63..0]). When the CAM block matches an input data value to an address location, it will assert the bit of the mbits bus that corresponds to a match address. For example, if there is a match at address location 5, bit 5 of the mbits bus will drive high. The unencoded address is valid 2 clock cycles after a data input is applied to the CAM block.
A 64-word encoded CAM block outputs a 6-bit (log2(64)) encoded match address (maddress[5..0]). The maddress bus displays the binary encoded match address for an input pattern.
The design and simulation files used in this example can be downloaded by clicking on the link below.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Reading from an Initialized Single-Match CAM block
CAM blocks can be initialized with a Hexadecimal file (.hex) with a memory initialization file (.mif), or you directly write to a CAM block. Figure 1 shows a simulation example for a CAM block that has been initialized with a MIF file. This example illustrates a pre-loaded CAM block that matches the data value of 4 at maddress = 3, a CAM block miss for a value of 0, a match for 999 at maddress = 63, a match for 202 at maddress = 52, a miss for 0, and a match for 11 at maddress = 0.
Figure 1. Vector Waveform File (read.vwf) Illustration
A read is initiated by driving the write enable signal (wren) low and applying the pattern input. If a match is found, the mfound signal will be asserted one clock cycle after an input pattern has been applied to the CAM block.
Note: This simulation example assumes that the CAM block was pre-loaded with initial.mif.
Writing to a Single-Match CAM Block
Figure 1 shows the process of writing to a 64-word CAM block.
A write operation is performed by asserting wren and write address (wraddress) for two clock cycles.
Altera's CAM blocks also have support for "don't care" bits. The simulation example illustrates writing "don't care" values to address location 0. "Don't care" write operations require three clock cycles to complete. The wrxused signal is asserted and held for three clock cycles to indicate that the CAM block will be writing a "don't care" value. Any bits in the wrx bus that are set to 1, indicate that bit position will be a "don't care" bit.
Figure 2. Vector Waveform File (write.vwf) Illustration
The above example writes a value of 15 (HEX "0000000F") to address location 0 and it sets a "don't care" value of 240 (HEX "000000F0") at location 0. Therefore, all values of "000000XF" will produce a match at location 0 (where 0 < X < F). This scenario is illustrated in the write.vwf simulation where patterns 255 and 79 drive maddress to 0. The simulation then writes a value of 9 at address location 1. When a data value of 9 is later applied to the CAM block, a match is found at maddress = 1.
Deleting a value from the CAM Block
Word values can be deleted from a CAM block through the wrdelete signal. To delete a value, wren and wrdelete should be held high for two clock cycles, during which wraddress should indicate the address containing the word that will be deleted. See Figure 3.
The delete.vwf simulation writes a value of 9 at address location 1. This value is then deleted by asserting wren and wrdelete for two clock cycles while wraddress = 1. The data value 9 no longer produces a match after the delete operation.
A delete operation is equivalent to setting a never match address. The address location that is a deleted never matches an input pattern until a data value is subsequently written to the CAM block at that address location.
Figure 3. Vector Waveform File (delete.vwf) Illustration
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