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Home > Support > Design Examples > Tcl > ModelSim Tcl Scripting Examples Print This Page Subscribe to Email ModelSim Tcl Scripting Examples Table 1 contains Tcl script examples that demonstrate a setup for Altera® libraries with the Mentor Graphics® ModelSim® SE and PE software. ModelSim-Altera edition and ModelSim-Altera Web Edition come with pre-compiled Altera libraries. Table 1 also contains examples that demonstrate a functional simulation for Altera memories and a timing simulation of a phase-locked loop (PLL) circuits inside Altera devices. For more information on Tcl and ModelSim, refer to the Mentor Graphics ModelSim Support (PDF) chapter of the Quartus® II Handbook (PDF). Table 1. ModelSim Tcl Script Examples Tcl Scripts Description Library Setup Script (Verilog HDL)  Library Setup Script (VHDL) These scripts demonstrate how to set up Altera libraries for the ModelSim SE or PE simulator using behavioral simulation library files available in the Quartus II software. These scripts are not intended for use with the ModelSim-Altera software. Altera Memory Behavioral Simulation This script demonstrates how to perform a simulation using Altera memory files, including RAM Initialization Files (.rif) and Hexadecimal (Intel-format) Files (.hex). PLL Post-Fit Timing Simulation This script demonstrates how to perform a PLL timing simulation using the +transport_int_delays and +transport_path_delays options. Rate This Page

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