TimeQuest Example: Basic SDC Example
The Synopsys Design Constraint (SDC) format provides a simple and easy method to constrain the simplest to the most complex designs. The following example provides the simplest SDC file content that constrains all clock (ports and pins), input I/O paths, and output I/O paths for a design. You can use the SDC file below as a template for any design. However, each design should contain a customized SDC file that individually constrains all clocks, input ports, and output ports.
# Global fMAX of 100 MHz
# All detected clocks will be constrained with a 100 MHz requirement
derive_clocks -period "100MHz"
# Automatically apply a generate clock on the output of phase-locked loops (PLLs)
# This command can be safely left in the SDC even if no PLLs exist in the design
derive_pll_clocks
# Constrain the input I/O path
set_max_delay -from [all_inputs] -to [all_registers] 1
set_min_delay -from [all_inputs] -to [all_registers] 2
# Constrain the output I/O path
set_max_delay -from [all_registers] -to [all_outputs] 3
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