TimeQuest Example: Constraining Maximum Skew
The TimeQuest Timing Analyzer does not support a single constraint that specifies maximum skew, but you can specify setup and hold times relative to a clock port to constrain a source synchronous interface. Figure 1 shows a simplified source-synchronous circuit that is used in the following example.
Figure 1. Source Synchronous Interface Diagram
Constraining Skew on an Output Bus
This example constrains the interface so that all bits of the data_out bus go off-chip between 2 and 3 ns after the clk_out signal. Assume that clk_in and clk_out have a period of 8 ns. The following equations and example shows how to create timing requirements that satisfy the timing relationships shown in Figure 2.
Figure 2. Source Synchronous Timing Diagram
These equations show how to compute the value for the set_output_delay -min command that creates the 2 ns hold requirement on the destination. For hold requirement calculations in which source and destination clocks are the same, <latch> - <launch> = 0.
latch - launch = 0 ns
output delay = latch - launch - 2 ns
output delay = -2 ns
These equations show how to compute the value for the set_output_delay command that creates the 3 ns setup requirement on the destination. For setup requirement calculations in which source and destination clocks are the same, <latch> - <launch> = clock period.
latch - launch = 8 ns
output delay = latch - launch - 3 ns
output delay = 5 ns
Finally, here are the constraints that bring all of the calculations together to apply the timing requirements to the source synchronous output.
set period 8.000
create_clock -period $period \
-name clk_in \
[get_ports clk_in]
derive_pll_clocks
set_output_delay -add_delay \
-clock ddr_pll_1_inst|altpll_component|pll|CLK[0] \
-reference_pin [get_ports clk_out] \
-min -2.000 \
[get_ports data_out*]
set_output_delay -add_delay \
-clock ddr_pll_1_inst|altpll_component|pll|CLK[0] \
-reference_pin [get_ports clk_out] \
-max [expr $period - 3.000] \
[get_ports data_out*]
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