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Home > Support > Design Examples > Synopsys VCS Print This Page Subscribe to Email Synopsys VCS Simulation Design Example Table 1 contains a gate-level timing simulation design example for use in designs for Altera® devices. Table 1. Simulation Design Example Function Design Entry Method Stratix® II Post-Fit Timing Simulation With Synopsys VCS Software The following icons indicate the entry mode(s) used for the example:  Altera hardware description language (AHDL)  VHDL  MAX+PLUS® II Graphic Editor  Verilog hardware description language (HDL)  Tool command language (Tcl)  Quartus® II development tool Related Links Simulation and Verification Resource Center Rate This Page

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