Verilog HDL: 1x64 Shift Register
This example describes a single-bit wide, 64-bit long shift register in Verilog HDL. Synthesis tools detect groups of shift registers and infer altshift_taps megafunction depending on the target device architecture.
Figure 1. 1x64 Shift Register Top-Level Diagram
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Table 1 lists the ports and gives a description for each.
| Table 1. 1x64 Shift Register Port Listing |
| Port Name |
Type |
Description |
clk |
Input |
Clock |
shift |
Input |
Shift enable input |
sr_in |
Input |
Shift register input |
sr_out |
Output |
Shift register output |
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