Verilog HDL: Interfacing a 267-MHz DDR2 SDRAM with an Arria II GX FPGA

This design demonstrates an Arria^® II GX device interfacing with 64-bit wide DDR2 SDRAM SODIMM running at 267 MHz.

The design features advanced I/O timing, board trace models, and the SignalTap^® II logic analyzer in Quartus^® II software. It is mapped to the Arria II GX Development Kit.

A walkthrough of the process is described in Volume 6, Section I of the External Memory Interface Handbook (PDF). Please refer to the Using DDR, DDR2, and DDR3 SDRAM in Arria II GX devices chapter for the full design guidelines and flow.

This design includes Tcl files for:

• Board trace models for the Arria II GX Development Kit
• Example driver "output ports" virtual pin assignments
• Pin location assignments for the Arria II GX Development Kit DDR2 SDRAM Interface

Download the files used in this example:

• Download emi_ddr2_aiigx_readme.txt 
• Download emi_ddr2_aiigx.zip

Related Links

• Arria II GX Development Kit
• Volume 6, Section I of the External Memory Interface Handbook (PDF)

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