This design demonstrates a 300-MHz, high-performance DDR3 SDRAM controller interfacing with 16-bit wide DDR3 SDRAM component at half-rate mode in an Arria® II GX FPGA.
The design features advanced I/O timing, board trace models, and the SignalTap® II logic analyzer in Quartus® II software. It is mapped to the Arria II GX Development Kit.
A walkthrough of the process is described in Volume 6, Section I of the External Memory Interface Handbook (PDF). Please refer to the Using DDR, DDR2, and DDR3 SDRAM in Arria II GX devices chapter for the full design guidelines and flow.
This design includes Tcl files for:
- Board trace models for the Arria II GX Development Kit
- Example driver "output ports" virtual pin assignments
- Pin location assignments for the Arria II GX Development Kit DDR3 SDRAM interface
Download the files used in this example:
- Download emi_ddr3_aiigx_readme.txt
- Download emi_ddr3_aiigx.zip
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These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
