This example describes a two-input, 8-bit adder/subtractor design in Verilog HDL. The design unit dynamically switches between add and subtract operations with an add_sub input port.
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Table 1 lists the ports in the adder/subtractor design.
| Table 1. Adder/Subtractor Port Listing | ||
| Port Name | Type | Description |
dataa[7:0], datab[7:0] |
Input | 8-bit data inputs |
add_sub |
Input | Input port to enable dynamic switching between add and subtract operations |
| clk | Input | Clock input |
result[8:0] |
Output | 8-bit data output and a carry/borrow MSB bit |
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