This example describes a two-input, 8-bit adder/subtractor design in Verilog HDL. The design unit dynamically switches between add and subtract operations with an
add_sub input port.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 lists the ports in the adder/subtractor design.
|Table 1. Adder/Subtractor Port Listing|
||Input||8-bit data inputs|
Input port to enable dynamic switching between add and subtract operations
||Output||8-bit data output and a carry/borrow MSB bit|
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.