This example describes a two-input, 8-bit, adder/subtractor design in Verilog HDL. The design unit multiplexes add and subtract operations with an addnsub input. Synthesis tools detect add and subtract units in HDL code that share inputs and whose outputs are multiplexed by a common signal. Software infers lpm_addsub megafunction for such add/subtract designs.
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Table 1 lists the ports and gives a description for each.
| Table 1. Adder/Subtractor Port Listing | ||
| Port Name | Type | Description |
a[7:0], b[7:0] |
Input | 8-bit data inputs to adder/subtractor |
addnsub |
Input | Multiplexing input for add and subtract operations |
result[8:0] |
Output | 8-bit output along with 1-bit carry/borrow |
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