This design demonstrates high-performance DDR2 SDRAM at 150 MHz with SOPC Builder integrated in a Cyclone® III FPGA Development Kit board.
This design includes a Synopsis design constraint (SDC) file for Cyclone III FPGA development kit board clock assignments (cycloneIII_3c120_generic.sdc), a Tcl file for pin location assignments for DDR2 devices, an interface on column I/Os, and an example Nios® II test program (DDR_TEST.c).
This design provides a walkthrough of the process presented in Volume 6, Section I of the External Memory Interface Handbook. Please refer to the Using High-Performance DDR, DDR2, and DDR3 SDRAM with SOPC Builder chapter for the full design guidelines and flow.
Download the files used in this example:
- Download emi_ddr2_ciii_sopcb_readme.txt
- Download emi_ddr2_ciii_sopcb.zip
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These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
