This example describes an 8-bit signed multiplier with registered I/O in Verilog HDL. Synthesis tools detect multiplier designs in HDL code and infer
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Table 1 lists the ports and gives a description for each.
|Table 1. Signed Multiplier Port Listing|
||Input||8-bit signed registered data inputs to multiplier unit. Input data is fed to the multiplier on each clock cycle.|
||Output||16-bit signed output of multiplier unit|
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