This example describes a 16-bit signed multiplier-adder design with pipeline registers in Verilog HDL. Synthesis tools are able to detect multiplier-adder designs in the HDL code and automatically infer the altmult_add megafunction to provide optimal results.
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The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 lists the ports in the signed multiplier-adder design.
| Table 1. Signed Multiplier-Adder Port Listing | ||
| Port Name | Type | Description |
dataa[15:0], datab[15:0],datac[15:0], datad[15:0] |
Input | 16-bit data inputs |
| clock | Input | Clock input |
| aclr | Input | Asynchronous clear input |
result[32:0] |
Output | 33-bit data output |
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