Verilog HDL: Single Clock Synchronous RAM
This example describes a single clock, synchronous, 128-bit x 8-bit RAM design with common read and write addresses in Verilog HDL. Synthesis tools detect single port RAM designs in HDL code and infer altsyncram or altdpram megafunctions depending on the target device architecture.
Figure 1. Single Clock Synchronous RAM Top-Level Diagram
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Table 1 lists the ports and gives a description for each.
| Table 1. Single Clock Synchronous RAM Port Listing |
| Port Name |
Type |
Description |
d[7:0] |
Input |
8-bit data input to RAM |
clk |
Input |
Clock |
a[6:0] |
Input |
7-bit address input to RAM |
we |
Input |
Write enable input |
q[7:0] |
Output |
8-bit data output of RAM |
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