Verilog HDL: Interfacing 533-MHz RLDRAM II in a Stratix IV FPGA

This design demonstrates a Stratix^® IV device interfacing with 36-bit wide RLDRAM II running at 533 MHz.

The design features advanced I/O timing, board trace models, and the SignalTap^TM II logic analyzer in Quartus^® II software. It is mapped to the Stratix IV E Development Kit. 

A walkthrough of the process is described in Volume 6, Section II of the External Memory Interface Handbook (PDF). Please refer to the Using RLDRAM II in Stratix III, Stratix IV, and Stratix V Devices chapter for the full design guidelines and flow.

This design includes Tcl files for:

• Example driver "output ports" virtual pin assignments
• Pin location assignments for the Stratix IV E Development Kit RLDRAM II Interface

Download the files used in this example:

• Download emi_rlii_siv_readme.txt 
• Download emi_rlii_siv.zip

Related Links

• Volume 6, Section II of the External Memory Interface Handbook (PDF)

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