This design demonstrates a Stratix® V device interfacing with two 64-bit wide DDR3 DIMMs running at 450 MHz. This implementation requires device resource sharing such as delay-locked loops (DLLs), phase-locked loops (PLLs), and on-chip termination (OCT) and requires extra steps to create the interfaces in a Quartus® II design project.
A walk-through of the process is described in Volume 6, Section II of the External Memory Interface Handbook (PDF). Please refer to the chapter, "Implementing Multiple Memory Interfaces Using UniPHY" in the handbook for the full design guidelines and flow.
Download the files used in this example:
- Download emi_Uniphy_multiple_ddr3_sv_readme.txt
- Download emi_uniphy_multiple_ddr3_sv.zip
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