This example describes an 8-bit unsigned multiplier-accumulator design with registered I/O ports and synchronous load in Verilog HDL. Synthesis tools are able to detect multiplier-accumulator designs in the HDL code and automatically infer the altmult_accum megafunction to provide optimal results.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 lists the ports in the unsigned multiplier-accumulator design.
| Table 1. Unsigned Multiplier-Accumulator Port Listing | ||
| Port Name | Type | Description |
dataa[7:0],datab[7:0] |
Input | 8-bit data inputs |
clk |
Input | Clock input |
aclr |
Input | Asynchronous clear input |
clken |
Input | Clock enable input |
| sload | Input | Synchronous load input |
adder_out[15:0] |
Output | 16-bit data output |
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
