Verilog HDL: 12 x 9 Firm Multiplier
This design implements 12 x 9 firm multiplication using DSP blocks. For more details on the design, refer to AN 306: Implementing Multipliers in FPGA Devices.
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Table 1 shows the 12 x 9 Firm Multiplier design example port listing.
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Table 1. 12 x 9 Firm Multiplier Port Listing
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Port Name
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Type
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Description
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data_a[8..0]
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Input
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9-bit signed input to the multiplier. New input can be sent to the multiplier every clock cycle.
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data_b[11..0]
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Input
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12-bit signed input to the multiplier. New input can be sent to the multiplier every clock cycle.
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clk
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Input
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Clock
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sclr
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Input
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Active high synchronous clear
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result[20..0]
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Output
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The output is a 21-bit signed value.
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