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Verilog HDL: 12 x 9 Firm Multiplier

Home > Support > Design Examples > Verilog HDL > Verilog HDL: 12 x 9 Firm Multiplier

This design implements 12 x 9 firm multiplication using DSP blocks. For more details on the design, refer to AN 306: Implementing Multipliers in FPGA Devices.

Download the file(s) used in this example:

  • Download 12 x 9_firm_mult.zip
  • Download 12 x 9 Firm Multiplier README File

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Table 1 shows the 12 x 9 Firm Multiplier design example port listing.

Table 1. 12 x 9 Firm Multiplier Port Listing

Port Name

Type

Description

data_a[8..0]

Input

9-bit signed input to the multiplier. New input can be sent to the multiplier every clock cycle.

data_b[11..0]

Input

12-bit signed input to the multiplier. New input can be sent to the multiplier every clock cycle.

clk

Input

Clock

sclr

Input

Active high synchronous clear

result[20..0]

Output

The output is a 21-bit signed value.


For more information on using this example in your project, go to:

  • AN 306: Techniques for Implementing Multipliers in Stratix, Stratix GX & Cyclone Devices
  • How to Use Verilog HDL Examples

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.

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