This design implements 12 x 9 firm multiplication using DSP blocks. For more details on the design, refer to AN 306: Implementing Multipliers in FPGA Devices.
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The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 shows the 12 x 9 Firm Multiplier design example port listing.
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Table 1. 12 x 9 Firm Multiplier Port Listing |
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Port Name |
Type |
Description |
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data_a[8..0] |
Input |
9-bit signed input to the multiplier. New input can be sent to the multiplier every clock cycle. |
|
data_b[11..0] |
Input |
12-bit signed input to the multiplier. New input can be sent to the multiplier every clock cycle. |
|
clk |
Input |
Clock |
|
sclr |
Input |
Active high synchronous clear |
|
result[20..0] |
Output |
The output is a 21-bit signed value. |
For more information on using this example in your project, go to:
- AN 306: Techniques for Implementing Multipliers in Stratix, Stratix GX & Cyclone Devices
- How to Use Verilog HDL Examples
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