Verilog HDL: Basic FIR Filter
This document describes the implementation of a basic finite impulse response (FIR) filter in Stratix™ devices. FIR filters are commonly used in digital signal processing (DSP) systems.
The basic structure of a FIR filter consists of a series of multiplications followed by an addition. A FIR filter operation can be represented by the following equation: 
This is where x(n) represents the sequence of input samples, h(n) represents the filter coefficients and L is the number of taps. A sample FIR filter with L=8 is shown in Figure 1.In Figure 1, eight samples of the input are used. Hence, it is called an 8-tap filter. Each of the registers provides a unit sample delay. The delayed inputs are multiplied with their respective filter coefficients and added together to produce the output.
Figure 1. Basic FIR Filter 
This particular design example has eight taps with 18-bit input samples and filter coefficients. Since a single DSP block can support up to four taps with 18-bit inputs, this design requires two DSP blocks. The input data is loaded serially into the DSP block. The shiftin/shiftout register chains inside the DSP blocks are used to create the appropriate delays. The filter coefficients are loaded from ROM implemented in TriMatrix™ memory blocks. For more details, see the Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook
Download the files used in this example:
Files included in download:
- basic_fir.v - Top-level design file
- bmult_add.v - Multiply-add function implementation using altmult_add megafunction
- badder.v - Adder to sum all eight multiply-add operations
- bbasic_fir.m - MATLAB script to verify functionality of design
Figure 2 illustrates the basic_fir top-level block diagram.
Figure 2. basic_fir Top-Level Block Diagram 
Table 1 shows the basic FIR filter design example port listing.
| Table 1. Basic FIR Filter Design Example Port Listing |
| Port Name |
Type |
Description |
| data_in[17..0] |
Input |
The input is an 18-bit signed integer that is shifted in serially using the shift registers of the DSP block. |
| clock |
Input |
Clock |
| clk_ena |
Input |
Clock-enable |
| reset |
Input |
Asynchronous reset |
| fir_result[37..0] |
Output |
Output of the FIR filter |
For more information on using this example, go to:
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