Verilog HDL: Behavioral Counter
This example describes an 8-bit loadable counter with count enable. The always construct, highlighted in red text, describes how the counter should behave.
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behav_counter.v
module behav_counter( d, clk, clear, load, up_down, qd);
// Port Declaration
input [7:0] d;
input clk;
input clear;
input load;
input up_down;
output [7:0] qd;
reg [7:0] cnt;
assign qd = cnt;
always @ (posedge clk)
begin
if (!clear)
cnt = 8'h00;
else if (load)
cnt = d;
else if (up_down)
cnt = cnt + 1;
else
cnt = cnt - 1;
end
endmodule
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