Verilog HDL: Instantiating a DFFE
This example describes how to generate a D flipflop with enable (DFFE) behaviorally with asynchronous preset and reset signals. Both the preset and reset signals are active low, controlling the output of the DFFE whenever either signal goes low.
For more information on using this example in your project, go to:
dffeveri.v
module dffeveri (q, d, clk, ena, rsn, prn);
// port declaration
input d, clk, ena, rsn, prn;
output q;
reg q;
always @ (posedge clk or negedge rsn or negedge prn) begin
//asynchronous active-low preset
if (~prn)
begin
if (rsn)
q = 1'b1;
else
q = 1'bx;
end
//asynchronous active-low reset
else if (~rsn)
q = 1'b0;
//enable
else if (ena)
q = d;
end
endmodule
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