Verilog HDL: Fully Variable Coefficient Soft Multiplier
This design implements 8-bit fully variable multiplication using M4K RAM blocks as look-up tables (LUTs). For more details on the design, refer to AN 306: Implementing Multipliers in FPGA Devices.
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Table 1 shows the Fully Variable Coefficient Soft Multiplier design example port listing.
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Table 1. Fully Variable Coefficient Soft Multiplier Port Listing
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Port Name
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Type
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Description
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data_a[7..0]
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Input
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8-bit unsigned input to the multiplier. New input can be sent to the multiplier every clock cycle.
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data_b[7..0]
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Input
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8-bit unsigned input to the multiplier. New input can be sent to the multiplier every clock cycle.
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clk
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Input
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Clock
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sclr
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Input
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Active high synchronous clear
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result[15..0]
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Output
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The output is a 32-bit unsigned value.
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