Verilog HDL: Semi-Parallel Fixed Coefficient Soft Multiplier
This design implements 16-bit input, 14-bit fixed coefficient semi-parallel multiplication using M512 RAM blocks as look-up tables (LUTs). For more details on the design, refer to AN 306: Implementing Multipliers in FPGA Devices.
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Table 1 shows the Semi-Parallel Fixed Soft Multiplier design example port listing.
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Table 1. Semi-Parallel Fixed Soft Multiplier Port Listing
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Port Name
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Type
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Description
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data_in[15..0]
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Input
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The input is a 16-bit signed value. New data can be updated every four clock cycles.
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sload_data
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Input
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Active high. Specifies a new multiplication operation and cancels any existing multiplication operation.
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clock
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Input
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Clock
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sclr
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Input
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Active high synchronous clear
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result[29..0]
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Output
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The output is a 30-bit signed value.
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result_valid
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Output
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Indicates when the output is the valid result of a complete multiplication. The signal will go high for the time that the output is valid.
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