Verilog HDL: Time Domain Multiplexed FIR Filter
A time domain multiplexed finite impulse response (FIR) filter is clocked n times as fast as the sample rate in order to reuse the same hardware. Since the same circuitry is being reused, this technique saves logic resources.
Figure 1 shows an 8-tap time domain multiplexed FIR filter with a time domain multiplex factor of two. Since the factor is two, only four multipliers are required to implement the 8-tap filter. In the first cycle of the 2x clock, the result of multiplying the input with the first four coefficients is computed; in the second cycle, the result of multiplying the input with the remaining four coefficients is computed. At the end of two cycles of 2x clock, these results are added to generate the overall output. The delay introduced by the register at the output ensures that the two results are aligned properly.
Figure 1. Block Diagram of Filter with Time Domain Multiplex Factor of n=2 
This design example describes the design of an 8-tap time domain multiplexed FIR filter with 18-bit coefficient and input resolution. Both the data and the coefficients are loaded in parallel. For more details, see the Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook.
Download the files used in this example:
Files in the download include:
- tdm_fir.v - Top-level design file
- clk_pll.v - PLL to generate 1x and 2x clock
- sr_shift_taps.v - Shift register implemented using altshift_taps Megafunction
- mult_add.v - Multiply-add function implementation using altmult_add Megafunction
- ext_adder.v - Adder to sum all eight multiply-add operations
- rom0.v, rom1.v, rom2.v, rom3.v - ROM used to store coefficients
- tdm_fir.m - MATLAB script to verify functionality of design
Figure 2 illustrates the tdm_fir top-level block diagram.
Figure 2. tdm_fir Top-Level Block Diagram 
Table 1 shows the Time Domain Multiplex FIR filter design example port listing.
| Table 1. Time Domain Multiplexed FIR Filter Design Example Port Listing Listing |
| Port Name |
Type |
Description |
| x0[17..0] |
Input |
Signed 18-bit input data shifted in serially using the shift register within the DSP block |
| clk |
Input |
Clock |
| clken |
Input |
Clock enable |
| reset |
Input |
Reset |
| load_data |
Output |
When asserted, the filter is ready to accept data on the x0 port |
| tdm_result[38..0] |
Output |
Output of the Time Domain Multiplexed FIR filter |
For more information on using this example, go to:
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