Verilog
The following Verilog examples provide instructions for implementing functions using Verilog hardware description language (HDL). For more information on Verilog HDL, refer to Quartus® II or MAX+PLUS® II software Help.
Verilog Embedded Processor Functions
 Standard Nios® II Hardware Design Example- Full-Featured Nios II Hardware Design Example
- Small Nios II Hardware Design Example
- Fast Nios II Hardware Design Example
- Low-Cost Nios II Hardware Design Example
Verilog Communications Functions
- Atlantic 1-to-2 Width Converter
- Atlantic 2-to-1 Width Converter
- Atlantic Loopback
Verilog Arithmetic Functions
- Adder/Subtractor
- Binary Adder Tree
- Ternary Adder Tree
- Parameterized Counter
- Behavioral Counter
Verilog Memory Functions
- Dual Clock Synchronous RAM
- Single Clock Synchronous RAM
- Parameterized RAM With Separate Input & Output Ports
- Quad Data Rate (QDR) SRAM Controller
Verilog Bus and I/O Functions
- High-Speed Differential I/O Capability
- Tri-State Instantiation
- Bidirectional Pin
Verilog Logic Functions
- 1 x 64 Shift Register
- 8 x 64 Shift Register With Taps
- Counter With Asynchronous Reset
- Instantiating a DFFE
- Synchronous State Machine
Verilog Digital Signal Processing (DSP) Functions
- Achieving Unity Gain in Block Floating Point IFFT+FFT Pair
- Coefficient Reload Finite Impulse Response (FIR) Filter
- Fast Fourier Transform (FFT) With 32K-Point Transform Length
- Signed Multiplier With Registered I/O
- Signed Multiply-Adder
- Unsigned Multiplier
- Unsigned Multiply-Accumulator
- 12 x 9 Firm Multiplier
- 12 x 12 Firm Multiplier
- Fully Variable Coefficient Soft Multiplier
- Hybrid Fixed Coefficient Soft Multiplier
- Hybrid Variable Coefficient Soft Multiplier
- Parallel Fixed Coefficient Soft Multiplier
- Parallel Variable Coefficient Soft Multiplier
- Semi-Parallel Fixed Coefficient Soft Multiplier
- Semi-Parallel Variable Coefficient Soft Multiplier
- Sum of Multiplication Fixed Coefficient Soft Multiplier
- Sum of Multiplication Variable Coefficient Soft Multiplier
- Discrete Cosine Transform (DCT)
- Basic FIR Filter
- Time Domain Multiplexed FIR Filter
- Polyphase Decimation FIR Filter
- Polyphase Interpolation FIR Filter
- Two-Dimensional FIR Filter
- Basic Infinite Impulse Response (IIR) Filter
- Butterworth IIR Filter
- Magnitude Function
Other Verilog Functions
- Creating a Hierarchical Design
- Instantiating MAX+PLUS II Primitives
How to Use Verilog HDL Examples
Altera provides Verilog HDL design examples as downloadable executable files or displayed as text in your web browser. Select the executable file link to download the file to your hard disk. To use Verilog HDL examples displayed as text in your Quartus II or MAX+PLUS II software, copy and paste the text from your web browser into the Quartus II or MAX+PLUS II software Text Editor. Make sure that the file name of the Verilog HDL design file (.v) corresponds to the entity name in the example. For instance, if the entity name is myram, save the file as myram.v.
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