This example describes a 256-bit x 8-bit dual-port ROM design with two address ports for read operations in VHDL. Synthesis tools are able to detect ROM designs in the HDL code and automatically infer the altsyncram or lpm_rom megafunctions depending on the target device architecture.
Figure 1. Dual-Port ROM Top-Level Diagram
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Table 1 lists the ports in the dual-port ROM design.
| Table 1. Dual-Port ROM Port Listing | ||
| Port Name | Type | Description |
addr_a[7:0], addr_b[7:0] |
Input | 8-bit read address inputs for port A and port B |
clk |
Input | Clock input |
q_a[7:0], q_b[7:0] |
Output | 8-bit data outputs for port A and port B |
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