This example describes an 8-bit Gray-code counter design in VHDL. The Gray code outputs differ in only one bit for every two successive values.
Figure 1. Gray Counter Top-Level Diagram
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 lists the ports in the Gray counter design.
| Table 1. Gray Counter Port Listing | ||
| Port Name | Type | Description |
clk |
Input | Clock input |
reset |
Input | Reset input |
| enable | Input | Enable input |
gray_count[7:0] |
Output | 8-bit data output |
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
