The QDR Consortium designed the quad data rate (QDR) SRAM architecture for high-performance communications systems such as routers and asynchronous transfer mode (ATM) switches. QDR SRAMs can handle the transfer of four data words through the SRAM in a single clock cycle.
You can implement the Altera® QDR SRAM controller reference design in a Stratix® or Stratix GX device to provide a simplified interface to a QDR SRAM device. The reference design includes VHDL source files, synthesis and place-and-route project files, and functional and timing simulation environments.
Download the QDR SRAM controller reference design:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Figure 1. QDR SRAM Controller Top-Level Block Diagram
For more information on using this example in your project, go to:
- AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices (PDF)
- How to Use VHDL Examples
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
