VHDL: QDR SRAM Controller
The QDR Consortium designed the quad data rate (QDR) SRAM architecture for high-performance communications systems such as routers and asynchronous transfer mode (ATM) switches. QDR SRAMs can handle the transfer of four data words through the SRAM in a single clock cycle.
You can implement the Altera® QDR SRAM controller reference design in a Stratix™ or Stratix GX device to provide a simplified interface to a QDR SRAM device. The reference design includes VHDL source files, synthesis and place-and-route project files, and functional and timing simulation environments.
Download the QDR SRAM controller reference design:
Figure 1. QDR SRAM Controller Top-Level Block Diagram
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