VHDL: Signed Multiplier
This example describes an 8-bit signed multiplier design in VHDL. Synthesis tools detect multiplier designs in HDL code and infer lpm_mult megafunction.
Figure 1. Signed Multiplier Top-Level Diagram
Download the files used in this example:
Table 1 lists the ports and gives a description for each.
| Table 1. Signed Multiplier Port Listing |
| Port Name |
Type |
Description |
a[7:0], b[7:0] |
Input |
8-bit data inputs to multiplier unit |
result[15:0] |
Output |
16-bit data output of multiplier unit |
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