VHDL: Signed Multiply-Accumulator
This example describes an 8-bit signed multiply-accumulator design with registered I/O ports in VHDL. Synthesis tools detect multiply-accumulator designs in HDL code and infer the altmult_accum megafunction.
Figure 1. Signed Multiply-Accumulator Top-Level Diagram
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Table 1 lists the ports and gives a description for each.
| Table 1. Signed Multiply-Accumulator Port Listing |
| Port Name |
Type |
Description |
a[7:0], b[7:0] |
Input |
8-bit registered data inputs to multiply-accumulator unit |
clk |
Input |
Clock |
accum_out[15:0] |
Output |
16-bit output of multiply-accumulator unit |
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