This example describes a 256-bit x 8-bit single-port ROM design with one address port for read operations in VHDL. Synthesis tools are able to detect ROM designs in the HDL code and automatically infer the altsyncram or lpm_rom megafunctions depending on the target device architecture.
Figure 1. Single-Port ROM Top-Level Diagram
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The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 lists the ports in the single-port ROM design.
Table 1. Single-Port ROM Port Listing |
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Port Name |
Type |
Description |
addr[7:0] |
Input |
8-bit read address |
clk |
Input |
Clock input |
q[7:0] |
Output |
8-bit data output |
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