VHDL: Three DDR3 ALTMEMPHY-Based Controllers Sharing DLL/PLL

This design features three DDR3 controllers on the top edge—two x16 interfaces and one x32 interface—operating at 400 MHz/800 Mbps in a Stratix^® IV FPGA.

This example design uses the ALTMEMPHY megafunction-based DDR3 SDRAM High-Performance Controller MegaCore^® function. In addition, one DLL and three static phase-locked loop (PLL) clocks are shared across all controllers. You can use this timing-closed design as an example showing feasibility for three controllers on one side of device with DLL/PLL sharing.

Download the files used in this example:

• Download three_ddr3_controllers_shared_sivgx_example_readme.txt
• Download three_ddr3_controllers_shared_sivgx_example.zip

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