VHDL: Unsigned Multiplier with Registered I/O
This example describes an 8-bit unsigned multiplier with registered I/O in VHDL. Synthesis tools detect multiplier designs in HDL code and infer lpm_mult megafunction.
Figure 1. Unsigned Multiplier Top-Level Diagram
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Table 1 lists the ports and gives a description for each.
| Table 1. Unsigned Multiplier Port Listing |
| Port Name |
Type |
Description |
a[7:0], b[7:0] |
Input |
8-bit unsigned registered data inputs to multiplier unit. Input data is fed to the multiplier on each clock cycle |
clk |
Input |
Clock |
aclr |
Input |
Asynchronous clear input |
result[15:0] |
Output |
16-bit registered data output of multiplier unit |
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