FPGA, CPLD, and ASIC solutions from Altera
  • Download Center
  • Literature
Sign in/register
myAltera Account
Welcome
  •   myAltera
  •   Logout
  • Products
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
    • Literature
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • DSP
    • External Memory
    • Embedded Processing
    • Transceivers
    • Parallel I/O
    • Signal Integrity
    • System Integration
  • Training
    • Training Courses
    • University Program
    • Webcasts & Videos
    • Demonstrations
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Database
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • User Communities/Forums
    • mySupport
  • About Altera
    • About Us
    • Environmental
    • Customer Successes
    • Partners
    • Newsroom
    • Investor Relations
    • Jobs
    • Contact Us
  • Buy Online
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
  • Entire Site
  • Part Number
  • Knowledge Database
  • Support & Technical Docs
  • Forums & Wiki
Username:  
Password:  
 
Forgot my username or password
Don't have myAltera account? Register Now.
Enter your email address:

VHDL: ZBT SRAM Controller

Home > Support > Design Examples > VHDL > VHDL: ZBT SRAM Controller

Zero bus turnaround (ZBT) SRAM with No Bus Latency (NoBL) memory is a synchronous burst SRAM with a simplified interface that fully uses the available bandwidth. ZBT SRAM devices use the full bandwidth because they do not require any turnaround or idle cycles between read and write operations. In contrast, standard synchronous burst SRAM devices require turnaround cycles, which significantly reduce the available bandwidth.

You can implement the Altera® ZBT SRAM controller reference design in a Stratix® (see figure 1 for the block diagram) or APEX™ II device (see figure 2 for the block diagram) to provide a simplified interface to ZBT SRAM. The reference design includes VHDL source files, synthesis and place and route project files, and functional and timing simulation environments.

The following ZBT SRAM controller reference designs are available for download:

  • ZBT Controller Reference Design for Stratix Devices
  • ZBT Controller Reference Design for APEX II Devices

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Figure 1. ZBT SRAM Controller System Level Block Diagram for Stratix & Stratix GX

Figure 1. ZBT SRAM Controller System Level Block Diagram for Stratix & Stratix GX

Figure 2. ZBT SRAM Controller System Level Block Diagram for APEX II

ZBT SRAM Controller System Level Block Diagram


For more information on using this example in your project, go to:

  • AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices
  • How to Use VHDL Examples

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.

Rate This Page


  • Products
    • MAX/MAX II
    • Stratix/Stratix GX
    • Nios II
  • Functionality
    • Arithmetic
    • External Memory Interfaces
    • On-Chip Memory
    • Bus & I/O Functions
    • Logic
    • Interfaces & Peripherals
    • DSP
    • Communications
    • PLL & Clocking
  • Design Entry
    • Quartus II
    • Tcl
    • VHDL
    • Verilog HDL
    • C Code
    • DSP Builder
    • TimeQuest
    • On-Chip Debugging
      • SignalTap II
  • Simulation Tools
    • Mentor Graphics ModelSim
    • Cadence NCsim
    • Synopsys VCS
  • Legacy Examples
    • Graphic Editor
    • AHDL
    Please give us feedback
    Products | End Markets | Technology | Training | Support | About Altera | Buy Online
    Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
    Copyright © 1995-2010 Altera Corporation. All Rights Reserved.
    Altera Forum
    Altera
    Forum
    Twitter
    Twitter
    RSS
    RSS
    Facebook
    Facebook
    Flickr
    Flickr
    YouTube
    YouTube
    Email Updates
    Email
    Updates