VHDL

The following examples provide instructions for implementing functions using VHDL. For more information on VHDL support, refer to Quartus^® II software Help.

For more examples of VHDL designs for Altera^® devices, refer to the Recommended HDL Coding Styles (PDF) chapter of the Quartus II Handbook. You can also access Verilog HDL examples from the language templates in Quartus II software. For additional hand-crafted techniques you can use to optimize design blocks for the adaptive logic modules (ALMs) in many Altera devices, refer to the Advanced Synthesis Cookbook: A Design Guide for Stratix II, Stratix III, and Stratix IV Devices (PDF)

VHDL Embedded Processor Functions

• Standard Nios^® II Hardware Design Example
• Full-Featured Nios II Hardware Design Example
• Small Nios II Hardware Design Example
• Fast Nios II Hardware Design Example
• Low-Cost Nios II Hardware Design Example

VHDL Arithmetic Functions

• Adder/Subtractor 
• Carry Look-Ahead Adder
• Down Counter (lpm_counter)
• Behavioral Counter
• Ripple-Carry Adder

VHDL Memory Functions

• Dual Clock Synchronous RAM 
• Single Clock Synchronous RAM 
• Single Clock Synchronous RAM with Asynhcronous Read Address 
• Cycle-Shared Dual-Port RAM (csdpram)
• Zero-Bus Turnaround (ZBT) Controller
• Quad Data Rate (QDR) SRAM Controller

VHDL Bus and I/O Functions

• Bidirectional Bus
• Tri-State Buses

VHDL Logic Functions

• 8x64 Shift Register with Taps 
• Counter with Synchronous Load 
• Preventing Unintentional Latch Creation 
• Instantiating a DFFE
• Instantiating a DFF Using lpm_dff

VHDL Digital Signal Processing (DSP) Functions

• VHDL Template for Inferring DSP Blocks in Stratix^® III and IV FPGAs
• Cyclic Prefix Insertion for OFDM Systems
• Viterbi Decoder With Node Synchronization 
• Signed Multiplier
• Signed Multiply-Accumulator
• Unsigned Multiplier with Registered I/O
• Unsigned Multiply-Adder

Other VHDL Functions

• Creating a Hierachical Design
• Converting a Hexadecimal Value to a Standard Logic Vector

How to Use VHDL Examples

Altera provides VHDL design examples as downloadable executable files or as text in your web browser. Click the executable file link to download the file to your hard disk. To use VHDL examples displayed as text in your Quartus II software (or legacy MAX+PLUS^®  II software), copy and paste the text from your web browser into the Text Editor. Make sure that the file name of the VHDL design file (.vhd) corresponds to the entity name in the example. For instance, if the entity name is myram, you should save the file as myram.vhd.

Design Examples Disclaimer

These design examples may only be used within Altera devices and remain the property of Altera Corporation. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.