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Triple Speed Ethernet (TSE) IP Core Resource Center

Home > Support > Intellectual Property > Triple Speed Ethernet

Altera provides extensive documentation and support for the Triple-Speed Ethernet MegaCore® function to help you quickly and easily develop and debug Ethernet applications such as line cards, NIC cards, and switches operating at 10/100 Mbps (fast Ethernet) or 1000 Mbps (gigabit Ethernet).

Literature

  • Triple-Speed Ethernet MegaCore Function User Guide (PDF)
  • MegaCore IP Library Release Notes and Errata (PDF)
  • Archive of Intellectual Property Release Notes
  • Archive of Intellectual Property Errata Sheets

Application Notes

  • AN 440: Accelerating Nios II Networking Applications (PDF)
  • AN 477: Designing RGMII Interface with HardCopy (PDF)
  • AN 483: Triple Speed Ethernet Data Path Reference Design (PDF)
  • AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices (PDF)
  • AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench (PDF)

Reference Designs

  • Triple-Speed Ethernet Data Path Reference Design

Altera Knowledge Database

The Knowledge Database provides support solutions, answers to frequently asked questions, and information about known issues regarding the Triple-Speed Ethernet MegaCore function.

See frequently viewed solutions:

  • In the Altera Triple-Speed Ethernet (TSE) MegaCore function, how is the PCS register address calculated?
  • How are the TSE register addresses in SOPC Builder calculated for the Altera Triple-Speed Ethernet (TSE) MegaCore function?
  • Why does the Altera Triple-Speed Ethernet (TSE) MegaCore function have an error during synthesis?
  • Which Triple-Speed Ethernet (TSE) MAC registers must be set to run a simulation?
  • Why is there a reconfig_clk frequency discrepancy between the device handbook and the Triple-Speed Ethernet (TSE) User Guide?

Find additional solutions on the Triple-Speed Ethernet MegaCore function.

Online Training Courses

  • 10/100/1000-Mbyte Ethernet Design with Altera Transceiver Devices
  • Chinese Version: 10/100/1000-Mbyte and 10-Gbyte Ethernet Design with Stratix® IV GX FPGAs

Development Kits

The following development kits are available for the Triple-Speed Ethernet MegaCore function:

  • Cyclone® III FPGA Development Kit
  • PCI Express Development Kit, Stratix II GX Edition
  • Stratix III FPGA Development Kit
  • Stratix IV GX FPGA Development Kit

Related Links

  • Altera® Forum
  • OpenCore Plus Support
  • Installation and Licensing Support Resources
  • IEEE 802.3 Standard Specification
  • Reduced Gigabit Media Independent Interface (RGMII) Specification
  • Avalon Interface Specifications
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